TLCS is a prefix applied to microcontrollers made by Toshiba. The product line includes multiple families of CISC and RISC architectures. Individual components generally have a part number beginning with "TMP". E.g. the TMP8048AP is a member of the TLCS_48 family.
The microcontrollers in the TLCS-90 family use a 8-bit/16-bit architecture reminiscent of the Z80. These are no longer advertised on the Toshiba web site. Z80 features present in the TLCS-90 include:
six 16-bit registers, three of which are 8-bit register pairs,
the combined parity/overflow flag,
the unusual, and instructions, and
the and memory copy instructions.
There are, however, significant differences. It omits the separate I/O address space of the Z80, but adds operations and several additional addressing modes:
one-byte "zero page" addressing of memory from FF00-FFFF16, and
indexed.
Also, the IX and IY registers are 20 bits wide, allowing the processor to address up to one megabyte of memory. Instructions are divided into one-byte basic and two-byte extended instructions. Opcodes E016 through FE16 are prefixes which begin an extended instruction. The instruction encoding is unusual in that the prefix specifies one operand of the extended instruction, and unlike the single-byte prefixes used by the Z80 or x86 architecture, may itself be followed by operand bytes. After the prefix bytes, the second opcode byte specifies the operation and second operand. For example, the instruction is encoded as, where the first two bytes specify the destination address, the third byte specifies the operation, and the fourth byte provides the source operand.
TLCS-870 family
The microcontrollers in the TLCS-870 family use a 8-bit/16-bit architecture inspired by the TLCS-90, but less like the Z80. The TLCS-870 is the original, with a 16-bit address space, which was extended in two different directions:
TLCS-870/X extends the architecture to 20 bits in an upward-compatible way.
TLCS-870/C retains the 16-bit address space, and provides a compatible assembly language, but changes the instruction encoding so that a different object code is required.
TLCS-870/C1 is an upward-compatible variant of the 870/C with minor extensions.
TLCS-900 family
The TLCS-900 family extend the TLCS-90 architecture to 32-bit registers and a 24-bit address bus. Most implementations have 16-bit internal data paths, like the MC68000, while the TLCS-900/H1 series is 32 bits wide internally. The instruction set is upward-compatible with the TLCS-90, although the binary encoding differs. The early models supported both a "minimum mode" where some registers were 16 bits wide and a "maximum mode" which had all 32-bit general purpose registers. Later models omitted the minimum mode.
Features and differences
Current TLCS processors offer some or all of the following features:
dual clock inputs and on-line clock switching by selecting different gear values, thus allowing either low-power low-frequency modes or high-performance high-frequency modes
As demand for these features differs widely depending on the requirements for a specific project, customers can choose from a wide range of different versions.
Development tools
Toshiba offers an ANSI C compatible C compiler and an assembler. Neither tool is available for free. The free Small Device C Compiler supports the TLCS-90. There is a to the TLCS-900 family. Alfred Arnold's The Macroassembler AS is a free assembler supporting the TLCS-47, TLCS-870, TLCS-90, TLCS-900 and TLCS-9000 families.
