Silicon on insulator


In semiconductor manufacturing, silicon on insulator technology is fabrication of silicon semiconductor devices in a layered silicon–insulator–silicon substrate, to reduce parasitic capacitance within the device, thereby improving performance. SOI-based devices differ from conventional silicon-built devices in that the silicon junction is above an electrical insulator, typically silicon dioxide or sapphire. The choice of insulator depends largely on intended application, with sapphire being used for high-performance radio frequency and radiation-sensitive applications, and silicon dioxide for diminished short-channel effects in other microelectronics devices. The insulating layer and topmost silicon layer also vary widely with application.

Industry need

SOI technology is one of several manufacturing strategies to allow the continued miniaturization of microelectronic devices, colloquially referred to as "extending Moore's Law". Reported benefits of SOI relative to conventional silicon processing include:
From a manufacturing perspective, SOI substrates are compatible with most conventional fabrication processes. In general, an SOI-based process may be implemented without special equipment or significant retooling of an existing factory. Among challenges unique to SOI are novel metrology requirements to account for the buried oxide layer and concerns about differential stress in the topmost silicon layer. The threshold voltage of the transistor depends on the history of operation and applied voltage to it, thus making modeling harder.
The primary barrier to SOI implementation is the drastic increase in substrate cost, which contributes an estimated 10-15% increase to total manufacturing costs.

SOI transistors

An SOI MOSFET is a metal-oxide-semiconductor field-effect transistor device in which a semiconductor layer such as silicon or germanium is formed on an insulator layer which may be a buried oxide layer formed in a semiconductor substrate. SOI MOSFET devices are adapted for use by the computer industry. The buried oxide layer can be used in SRAM designs. There are two types of SOI devices: PDSOI and FDSOI MOSFETs. For an n-type PDSOI MOSFET the sandwiched p-type film between the gate oxide and buried oxide is large, so the depletion region can't cover the whole p region. So to some extent PDSOI behaves like bulk MOSFET. Obviously there are some advantages over the bulk MOSFETs. The film is very thin in FDSOI devices so that the depletion region covers the whole film. In FDSOI the front gate supports fewer depletion charges than the bulk so an increase in inversion charges occurs resulting in higher switching speeds. The limitation of the depletion charge by the BOX induces a suppression of the depletion capacitance and therefore a substantial reduction of the subthreshold swing allowing FD SOI MOSFETs to work at lower gate bias resulting in lower power operation. The subthreshold swing can reach the minimum theoretical value for MOSFET at 300K, which is 60mV/decade. This ideal value was first demonstrated using numerical simulation. Other drawbacks in bulk MOSFETs, like threshold voltage roll off, etc. are reduced in FDSOI since the source and drain electric fields can't interfere due to the BOX. The main problem in PDSOI is the "floating body effect " since the film is not connected to any of the supplies.

Manufacture of SOI wafers

SiO2-based SOI wafers can be produced by several methods:
An exhaustive review of these various manufacturing processes may be found in reference

Microelectronics industry

Research

The silicon-on-insulator concept dates back to 1964, when it was proposed by C.W. Miller and P.H. Robinson. In 1979, a Texas Instruments research team including A.F. Tasch, T.C. Holloway and Kai Fong Lee fabricated a silicon-on-insulator MOSFET. In 1983, a Fujitsu research team led by S. Kawamura fabricated a three-dimensional integrated circuit with SOI CMOS structure. In 1984, the same Fujitsu research team fabricated a 3D gate array with vertically-stacked dual SOI/CMOS structure using beam recrystallization. The same year, Electrotechnical Laboratory researchers Toshihiro Sekigawa and Yutaka Hayashi fabricated a double-gate MOSFET, demonstrating that short-channel effects can be significantly reduced by sandwiching a fully depleted SOI device between two gate electrodes connected together. In 1986, Jean-Pierre Colinge at HP Labs fabricated SOI NMOS devices using 90 nm thin silicon films.
In 1989, Ghavam G. Shahidi initiated the SOI Research Program at the IBM Thomas J Watson Research Center. He was the chief architect of SOI technology at IBM Microelectronics, where he made fundamental contributions, from materials research to the development of the first commercially viable devices, with the support of his boss Bijan Davari. Shahidi was a key figure in making SOI CMOS technology a manufacturable reality. In the early 1990s, he demonstrated a novel technique of combining silicon epitaxial overgrowth and chemical mechanical polishing to prepare device-quality SOI material for fabricating devices and simple circuits, which led to IBM expanding its research program to include SOI substrates. He was also the first to demonstrate the power-delay advantage of SOI CMOS technology over traditional bulk CMOS in microprocessor applications. He overcame barriers preventing the semiconductor industry's adoption of SOI, and was instrumental in driving SOI substrate development to the quality and cost levels suitable for mass-production.
In 1994, an IBM research team led by Shahidi, Bijan Davari and Robert H. Dennard fabricated the first sub-100 nanometer SOI CMOS devices. In 1998, a team of Hitachi, TSMC and UC Berkeley researchers demonstrated the FinFET, which is a non-planar, double-gate MOSFET built on an SOI substrate. In early 2001, Shahidi used SOI to developed a low-power RF CMOS device, resulting in increased radio frequency, at IBM.

Commercialization

Shahidi's research at IBM led to the first commercial use of SOI in mainstream CMOS technology. SOI was first commercialized in 1995, when Shahidi's work on SOI convinced John Kelly, who ran IBM's server division, to adopt SOI in the AS/400 line of server products, which used 220 nm CMOS with copper metallization SOI devices. IBM began to use SOI in the high-end RS64-IV "Istar" PowerPC-AS microprocessor in 2000. Other examples of microprocessors built on SOI technology include AMD's 130 nm, 90 nm, 65 nm, 45 nm and 32 nm single, dual, quad, six and eight core processors since 2001.
In late 2001, IBM was set to introduce 130 nanometer CMOS SOI devices with copper and low-κ dielectric for the back end, based on Shahidi's work. Freescale adopted SOI in their PowerPC 7455 CPU in late 2001. Currently, Freescale is shipping SOI products in 180 nm, 130 nm, 90 nm and 45 nm lines. The 90 nm PowerPC- and Power ISA-based processors used in the Xbox 360, PlayStation 3, and Wii use SOI technology as well. Competitive offerings from Intel however continue to use conventional bulk CMOS technology for each process node, instead focusing on other venues such as HKMG and tri-gate transistors to improve transistor performance. In January 2005, Intel researchers reported on an experimental single-chip silicon rib waveguide Raman laser built using SOI.
As for the traditional foundries, on July 2006 TSMC claimed no customer wanted SOI, but Chartered Semiconductor devoted a whole fab to SOI.

Use in high-performance radio frequency (RF) applications

In 1990, Peregrine Semiconductor began development of an SOI process technology utilizing a standard 0.5 μm CMOS node and an enhanced sapphire substrate. Its patented silicon on sapphire process is widely used in high-performance RF applications. The intrinsic benefits of the insulating sapphire substrate allow for high isolation, high linearity and electro-static discharge tolerance. Multiple other companies have also applied SOI technology to successful RF applications in smartphones and cellular radios.

Use in photonics

SOI wafers are widely used in silicon photonics. The crystalline silicon layer on insulator can be used to fabricate optical waveguides and other optical devices, either passive or active. The buried insulator enables propagation of infrared light in the silicon layer on the basis of total internal reflection. The top surface of the waveguides can be either left uncovered and exposed to air, or covered with a cladding, typically made of silica.