SPARC T5


SPARC T5 is the fifth generation multicore microprocessor of Oracle's SPARC T-Series family. It was first presented at Hot Chips 24 in August 2012, and was officially introduced with the Oracle SPARC T5 servers in March 2013. The processor is designed to offer high multithreaded performance, as well as high single threaded performance from the same chip.
The processor uses the same SPARC S3 core design as its predecessor, the SPARC T4 processor, but is implemented in a 28 nm process and runs at 3.6 GHz. The S3 core is a dual-issue core that uses dynamic threading and out-of-order execution, incorporates one floating point unit, one dedicated cryptographic unit per core.
The 64-bit SPARC Version 9 based processor has 16 cores supporting up to 128 threads per processor, and scales up to 1,024 threads in an 8 socket system. Other changes include the support of PCIe version 3.0 and a new cache coherence protocol.

SPARC T5 and T4 compared

This chart shows some differences between the T5 and T4 processor chips.
ProcessorSPARC T5SPARC T4
Max chips per system84
Cores per chip168
Max threads per chip12864
Frequency3.6 GHz2.85-3.0 GHz
Shared Level 3 cache8 MB4 MB
MCUs per chip42
Transfer rate per MCU12.8 Gbit/s6.4 Gbit/s
Process Technology28 nm40 nm
Die size478 mm2403 mm2
PCIe Version3.02.0

The SPARC T5 also introduces a new power management feature that consists of hardware support in the processor, and the software that allows system administrator to use the feature. Users select the policy how the system responds to over-temperature and over-current events. The dynamic voltage and frequency scaling policy can be set to maintain peak frequency, or to trade off between performance and power consumption.

SPARC T5 in systems

The SPARC T5 processor is used in Oracle's entry and mid-size SPARC T5-2, T5-4, and T5-8 servers. All servers use the same processor frequency, number of cores per chip and cache configuration.
The T5 processor includes a crossbar network that connects the 16 cores with the L2 caches to the shared L3 cache. Multiprocessor cache coherence is maintained using a directory-based protocol. The design scales up to eight sockets without additional silicon. The snoopy based protocol used in SPARC T4 systems was replaced in order to reduce memory latency and reduce coherency bandwidth consumption.