An Advanced Encryption Standard instruction set is now integrated into many processors. The purpose of the instruction set is to improve the speed of applications performing encryption and decryption using Advanced Encryption Standard. They are often implemented as instructions implementing a single round of AES along with a special version for the last round which has a slightly different method.
* Mobile: all Core i7 and Core i5. Several vendors have shipped BIOS configurations with the extension disabled; a BIOS update is required to enable them.
AES support with unprivileged processor instructions is also available in the latest SPARC processors and in latest ARM processors. The SPARC T4 processor, introduced in 2011, has user-level instructions implementing AES rounds. These instructions are in addition to higher level encryption commands. The ARMv8-Aprocessor architecture, announced in 2011, including the ARM Cortex-A53 and A57 also have user-level instructions which implement AES rounds. In August 2012, IBM announced that the then-forthcoming Power7+ architecture would have AES support. The commands in these architectures are not directly equivalent to the AES-NI commands, but implement similar functionality. IBM z9 or later mainframe processors support AES as single-opcode AES ECB/CBC instructions via IBM's CryptoExpress hardware. These single-instruction AES versions are therefore easier to use than Intel NI ones, but may not be extended to implement other algorithms based on AES round functions.
SPARC T3 and later processors have hardware support for several cryptographic algorithms, including AES.
Cavium Octeon MIPS All Cavium Octeon MIPS-based processors have hardware support for several cryptographic algorithms, including AES using special coprocessor 3 instructions.
Performance
In AES-NI Performance Analyzed, Patrick Schmid and Achim Roos found "impressive results from a handful of applications already optimized to take advantage of Intel's AES-NI capability". A performance analysis using the Crypto++security library showed an increase in throughput from approximately 28.0 cycles per byte to 3.5 cycles per byte with AES/GCM versus a Pentium 4 with no acceleration.
Supporting software
Most modern compilers can emit AES instructions. Much security and cryptography software supports the AES instruction set, including the following core infrastructure:
